1. Missing or mismatched drill data
Symptom: holes appear in the CAD but not in the package, or the drill file is in inches while the Gerber is in millimetres.
Fix: state units in the file and on the drawing, keep plated and non-plated holes separate, and check that the hole count in the drill file matches the CAD report.
2. Solder mask over pads
Symptom: a mask opening is missing or offset, so a pad is covered or partially covered.
Fix: use the mask layer as a negative image and check it independently of the copper. A covered pad is invisible until assembly, when the part will not wet.
3. Mask slivers
Symptom: a strip of mask narrower than the process can hold between two openings.
Fix: widen the dam to at least 0.1 mm, or merge the openings where the design allows. Slivers lift during development and leave exposed copper.
4. Annular ring below spec
Symptom: the copper pad around a hole is too small for the drill tolerance, especially on small vias.
Fix: increase the pad, reduce the drill, or move the via. The ring has to survive drill registration, not just the nominal drill size.
5. Copper too close to the board edge
Symptom: traces or planes run to the routed edge, and the router exposes or nicks them.
Fix: keep copper back from the outline by the fabrication allowance, and route the edge clearance rule into the DRC so it cannot be forgotten.
6. Features below the process window
Symptom: 0.05 mm gaps, 0.1 mm mechanical holes, or a 20:1 aspect ratio.
Fix: compare the design against the published capability before routing — 0.075 mm line and space, 0.15 mm mechanical holes, 15:1 aspect ratio, 0.1–6.0 mm thickness — rather than after the Gerber is checked.
7. Unconnected copper islands
Symptom: a pour or a trace that connects to nothing, isolated by a clearance.
Fix: delete it, or connect it deliberately. An isolated island charges during plating, etches unevenly and can create a reliability question that nobody can answer later.
8. Missing panel and tooling data
Symptom: no fiducials, no tooling holes, no coupons, no array definition.
Fix: define the panel in the fabrication drawing: rails, fiducials, tooling holes, V-score or tab positions, and where the impedance coupon sits. The assembly line needs the same information to build its fixture.
The pattern behind all eight
Every one is a mismatch between the CAD file and the process, and every one is visible before tooling. A DFM review that walks the data package against the published capability finds them in an hour; a re-spin after tooling costs weeks.
The limits to check against are on the capability page; the sequence they belong to is in the process note, and the panel rules in the panelisation note.



