Impedance is a geometry problem
A 50 Ω trace is not a property of the net name; it is the result of trace width, dielectric thickness, dielectric constant and the reference plane distance. Change any one of them and the impedance moves. That is why a stackup drawing plus a target value is the minimum information a fabricator needs.
Start from the stackup
Fix the board thickness and layer count first, then allocate dielectric thickness between signal and reference layers. Keeping the same dielectric build across lots matters more than a tight nominal value: a repeatable 50 Ω ±10% is easier to defend than a nominal 50 Ω that drifts with each panel.
- Keep reference planes continuous under impedance-controlled nets; a slot or split forces the return current to detour and changes the local impedance.
- Avoid changing reference layers mid-route unless the design accounts for the via transition.
- Ask for the fabricator's standard build before choosing a non-standard dielectric.
What we hold on the line
Our process supports 1–38 layers, 0.075 mm trace and spacing, 0.1 mm laser vias and outer copper up to 20 oz. For impedance-controlled work we build coupons per lot and measure with TDR; ±10% is the normal production window, and ±5% is quoted case by case after reviewing the stackup.
Where designs usually fail
- Impedance target without a stackup — the fabricator has to guess the dielectric build, and the first article misses.
- Reference plane split under a connector — the impedance is correct on the coupon and wrong on the board.
- Mixed finishes on one panel — ENIG and HASL have different thickness implications for fine-pitch parts.
The cheapest fix is a DFM review before tooling. Send the Gerber set and the impedance table; we answer with the stackup we would build and the tolerances we can hold.
